Field of the Invention
The present invention relates to an electronic timepiece.
Background Art
In a case where an analog display electronic timepiece is stored or displayed while being normally operated, a mechanism for counting the time is driven. Consequently, in some cases, battery life is no longer preserved within approximately two years. Therefore, in some cases, in order to prolong the battery life, a crown is pulled out and a mode for stopping an operation of the electronic timepiece is used in a store. However, even in this case, a signal line to check whether the crown is turned on or turned off is pulled up or pulled down, thereby consuming current power. Hereinafter, this configuration will be described with reference to FIG. 10.
FIG. 10 is a circuit diagram illustrating a configuration of a crown switch detection circuit 500 in the electronic timepiece in the related art. In the circuit illustrated in FIG. 10, a reference potential Vdd is a voltage higher than a power source Vss. In FIG. 10, a crown switch 511 is inserted between one end of a signal line 512 and the reference potential Vdd. The other end of the signal line 512 is connected to a crown switch detection terminal 515 via an inverter 513 and an inverter 514.
As a pull-down resistor, an N-channel MOS transistor 516 and an N-channel MOS transistor 517 are inserted between the signal line 512 and the power source Vss. On-resistance of the N-channel MOS transistor 516 is greater than on-resistance of the N-channel MOS transistor 517. A gate of the N-channel MOS transistor 516 is connected to the reference potential Vdd. An output signal of a NAND gate 519 is supplied to a gate of the N-channel MOS transistor 517.
An output signal of the inverter 514 is supplied to one input terminal of the NAND gate 519. A system reset signal SRX is supplied from a system reset terminal 518 to the other input terminal of the NAND gate 519. The system reset signal SRX is supplied from a control circuit 4 (FIG. 2).
When the crown is in an inserted state, the crown switch 511 is turned off. When the crown switch 511 is turned off, one end of the signal line 512 is opened. In this case, since the gate of the N-channel MOS transistor 516 is the reference potential Vdd, the N-channel MOS transistor 516 is turned on. Accordingly, the signal line 512 is pulled down to a low level by the N-channel MOS transistor 516. In this manner, a crown switch detection signal K1IN output from the crown switch detection terminal 515 is in a low level.
At the time of initial setting, the system reset signal SRX output from the system reset terminal 518 is in a low level, and power-on reset is performed. If the system reset signal SRX output from the system reset terminal 518 is in a low level, the output signal of the NAND gate 519 is in a high level, thereby turning on the N-channel MOS transistor 517. If the N-channel MOS transistor 517 is turned on, the N-channel MOS transistor 517 functions as the pull-down resistor, and the signal line 512 is pulled down to a low level.
During normal operation, the system reset signal SRX output from the system reset terminal 518 is in a high level. In addition, the crown is in a pressed state, and thus, the crown switch 511 is turned off. Since the N-channel MOS transistor 516 is always turned on, the signal line 512 is connected via the N-channel MOS transistor 516, and is pulled down to a low level, thereby bringing the output signal of the inverter 514 to a low level. In addition, at the time of the normal operation, the system reset signal SRX output from the system reset terminal 518 is in a high level. Therefore, the output signal of the NAND gate 519 is in a high level. The N-channel MOS transistor 517 is turned on, and the signal line 512 is pulled down to a low level.
In this way, during normal operation, the signal line 512 is pulled down to a low level by the N-channel MOS transistor 516 and the N-channel MOS transistor 517, thereby bringing the crown switch detection signal K1IN output from the crown switch detection terminal 515 into a low level. The ON-resistance of the N-channel MOS transistor 517 is smaller than the ON-resistance of the N-channel MOS transistor 516. Accordingly, the N-channel MOS transistor 517 dominantly functions as the pull-down resistor. In this way, the signal line 512 is pulled down by the N-channel MOS transistor 517 having the smaller ON-resistance. Therefore, the electronic timepiece can be hardly affected by noise.
Next, if the crown is pulled out while the system is operated, the crown switch 511 is turned on. If the crown switch 511 is turned on, one end of the signal line 512 is connected to the reference potential Vdd via the crown switch 511. This brings the signal line 512 into a high level.
If the signal line 512 is in a high level, an output of the inverter 514 is in a high level, and the crown switch detection signal K1IN output from the crown switch detection terminal 515 is in a high level. In addition, while the system is operated, the system reset signal SRX is in a high level. Accordingly, the output signal of the NAND gate 519 is in a low level, and the N-channel MOS transistor 517 is turned off. Therefore, the N-channel MOS transistor 517 no longer functions as the pull-down resistor.
In this case, although the N-channel MOS transistor 516 is turned on, the ON-resistance of the N-channel MOS transistor 516 is great. Therefore, a small amount of currents flows via the N-channel MOS transistor 516.
In this way, in the crown switch detection circuit 500 of the electronic timepiece in the related art illustrated in FIG. 10, if the crown is pulled out, the crown switch 511 is turned on. One end of the signal line 512 is connected to the reference potential Vdd via the crown switch 511, and the crown switch detection signal K1IN output from the crown switch detection terminal 515 is in a high level. A control circuit of the timepiece detects that the crown switch detection signal K1IN is in a high level, and employs a mode for stopping an operation of the timepiece. In this mode, time adjustment can be done by rotating the crown. In addition, it is possible to prolong the battery life by storing or displaying the timepiece which employs the mode for stopping the operation of the timepiece.
However, in the crown switch detection circuit 500 of the electronic timepiece in the related art illustrated in FIG. 10, even while the crown switch 511 is turned on and the signal line 512 is in a high level, the N-channel MOS transistor 516 used for pull-down is turned on. Consequently, currents flow via the N-channel MOS transistor 516. An ON-resistance value of the N-channel MOS transistor 516 is great. Thus, a small amount of currents flows via the N-channel MOS transistor 516. However, in a case where the timepiece is displayed after the crown is pulled out, the small amount of currents also affects the battery life.
In order to further reduce the currents flowing in the N-channel MOS transistor 516 when the crown switch 511 is turned on, it is conceivable to increase the ON-resistance of the N-channel MOS transistor 516. However, if the ON-resistance value is increased in the N-channel MOS transistor 516 functioning as the pull-down resistor, a problem arises in that a chip area increases. Therefore, as disclosed in JP-A-2001-109734, a proposal is suggested in which a switching element for driving a pull-down function or a pull-up function is periodically turned on and off.
As disclosed in JP-A-2001-109734, in a case where the switch for pull-down or pulled-up is periodically turned on and off, if a time required for turning on the switch for pull-down or pulled-up is shortened, an advantageous effect increases in reducing current consumption. For example, if the switch is turned on as much as a width of 122 usec per frequency of 128 Hz, when a power source voltage is 1.55 V and the ON-resistance is 2 M?, current consumption of 12.1 nA can be realized while the switch is turned on as much as the width of 122 usec. However, even in this case, the current consumption is approximately 12 nA, and there is a need to further reduce the current consumption. In this case, it is necessary to more quickly switch the switching element for pull-down or pull-up. In a case of the electronic timepiece, it is considered that a switching signal of the switching element is formed of an oscillation signal of a quartz resonator. A signal having a frequency which is equal to or smaller than an oscillation frequency of the quartz resonator can be formed by dividing the oscillation signal of the quartz resonator. However, it is necessary to generate the switching signal for quickly switching the switching element by combining each signal of a frequency divider circuit. Parasitic capacitance of a transistor configuring a combination circuit thereof is charged and discharged using a quick signal. Consequently, there is a problem in that the charging and discharging current increases the current consumption.